The present invention relates generally to electronic protection circuits, and more particularly to thermal shutdown circuits.
Modern electronic circuits contain thermal shutdown circuits for reducing power dissipation and overheating in electronic circuits. An example of such a thermal shutdown circuit 100 is shown in FIG. 1.
FIG. 1 is a schematic of a conventional thermal shutdown circuit (100). The thermal shutdown circuit 100 includes resistors R1 through R5, transistors Q1 through Q5, transistors M1 through M3, and inverters X1 through X3.
Resistor R1 is coupled between node VREG and node N1. An emitter of transistor Q1 is coupled to node N1. A base and a first collector of transistor Q1 is coupled to node N2. A second collector of transistor Q1 is coupled to node N3. A collector of transistor Q2 is coupled to node N2. A base of transistor Q2 is coupled to node VBG. An emitter of transistor Q2 is coupled to node N4. Resistor R2 is coupled between node N4 and a voltage reference such as ground (xe2x80x9cgroundxe2x80x9d). A collector and a base of transistor Q3 are coupled to node N3. An emitter of transistor Q3 is coupled to ground. Resistor R3 is coupled between node VREG and node N5. Resistor R4 is coupled between node N5 and node N6. A collector of transistor Q4 is coupled to node N6. A base of transistor Q4 is coupled to node N3. An emitter of transistor Q4 is coupled to node N7. Resistor R5 is coupled between node N7 and ground. A source of transistor M1 is coupled to node VREG. A drain of transistor M1 is coupled to node N5. A gate of transistor M1 is coupled to node TSH.
An emitter of transistor Q5 is coupled to node VREG. A base of transistor Q5 is coupled to node N6. A collector of transistor QS is coupled to node N8. A drain and a gate of transistor M2 are coupled to node N8. A source of transistor M2 is coupled to ground. A gate of transistor M3 is coupled to node N8. A source of transistor M3 is coupled to ground. A drain of transistor M3 is coupled to current source X11. An input of inverter X1 is coupled to current source X11. An output of inverter X1 is coupled to node N9. An input of inverter X2 is coupled to node N9. An output of inverter X2 is coupled to node N10. An input of inverter X3 is coupled to node N10. An output of inverter X3 is coupled to node TSH.
Transistor Q2 is used to develop a reference current. The reference current is used to set a voltage drop across resistors R3 and R4. Transistor Q5 is turned off (i.e., does not conduct current) when the VBE of transistor Q5 is greater than the voltage drop across resistors R3 and R4. The VBE of transistor Q5 is decreased in response to an increase in temperature. When the VBE of transistor Q5 is equal to the voltage drop across resistors R3 and R4, transistor Q5 is activated and draws a current. Transistor Q5 induces a current in transistor M2, which is reflected in transistor M3. The current flowing through transistor M3 pulls the input of inverter X1 low, which drives the output (TSH) of inverter X3 high. The signal at node TSH is used to turn off circuitry that potentially produces excessive amounts of heat.
The present invention is directed towards a circuit for providing a thermal shutdown signal in response to an overtemperature condition. The thermal shutdown circuit is typically implemented in the same die as the circuitry that is to be protected. The thermal shutdown circuit provides a first current in response to a change in temperature when a VBE associated with a transistor decreases below a predetermined level. The first current is mirrored to provide a scaled current. A thermal shutdown signal is activated when the scaled current becomes greater than a reference current. The first current is increased in response to the activated thermal shutdown signal such that the thermal shutdown circuit is deactivated at a temperature that is lower than the temperature at which the circuit is activated. The thermal shutdown circuit is deactivated when the temperature of the die decreases.
A more complete appreciation of the present invention and its improvements can be obtained by reference to the accompanying drawings, which are briefly summarized below, to the following detailed description of illustrated embodiments of the invention, and to the appended claims.